1. Field of the Invention
The present invention relates generally to a semiconductor memory device and a test method of the same, and the invention is applied, for example, to a memory chip in which a NOR flash memory is mounted.
2. Description of the Related Art
Conventionally, in a semiconductor memory device such as a memory chip in which a NOR flash memory is mounted, it is necessary to conduct a screening test to determine whether the flash memory can normally function or not (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 2006-85769). However, this screening test requires a very long time with respect to one memory chip (1 chip), leading to an increase in cost. To avoid this problem, a BIST test, which is implemented by BIST (Built-In Self-Test), is performed to carry out the screening test by a test circuit that is built in the memory chip itself. The BIST is a methodology in which a scheme (hereinafter referred to as “test circuit”) for testing a to-be-tested object is activated by a trigger (e.g. a command) that is delivered from an external input provided in the to-be-tested object, and a determination result of the test can be received by an external output provided in the to-be-tested object. In other words, the BIST refers to the scheme for executing a self-test and an interface that makes use of this scheme.
The test circuit includes circuits of a read operation system for inputting an address and reading cell data, and circuits of an auto-operation system for inputting a command and executing a write operation and an erase operation in the flash memory. Moreover, in the circuits of the read operation system and the circuits of the auto-operation system, a control circuit and a sense amplifier circuit are independently controlled. This is intended to enable read-out (“dual read”) of a block which is different from a block that is the object of the auto-operation.
However, at the time of the BIST test, write/erase of a semiconductor memory is executed by an auto-operation control circuit, and a read operation (verify operation) is executed by an auto-operation sense amplifier circuit, thereby carrying out read-out of cell data and screening of a chip. In other words, at the time of the BIST test, the screening test is performed only by the circuits (auto-operation control circuit and auto-operation sense amplifier circuit) of the auto-operation system.
For this reason, in the conventional screening test, the circuits of the read operation system, namely, a read control circuit and a read sense amplifier circuit, could not be implemented by the BIST scheme. Hence, even in a case where a circuit defect occurs in the circuits of the read operation system, it is not possible to screen the read control circuit and read sense amplifier circuit. As a result, as regards the screening of the read control circuit and read sense amplifier circuit, another test needs to be performed in a subsequent step of the BIST test, leading to an increase in test time and test cost.